NEW YORK — What happened Foundry data released across European and Asian manufacturing hubs confirms that High-NA Extreme Ultraviolet (EUV) lithography systems have successfully begun processing initial test wafers for sub-2nm equivalent nodes.
Why it matters Lithography tools print the microscopic circuitry that defines modern microprocessors. Standard low-NA EUV tools reached physical limits that required multi-patterning—splitting a single circuit layer across two or three separate photolithography passes, which drove up defect risks. High-NA EUV prints finer lines in a single pass, but the new optical design cuts the printable area on the wafer in half, forcing foundries to rethink how large chips are laid out.
Deep dive High-NA systems raise the numerical aperture from 0.33 to 0.55 using massive anamorphic mirrors. Anamorphic optics magnify the horizontal and vertical axes unequally (4x in one direction, 8x in the other) to keep angles manageable on the photomask.
Because the maximum reticle size cannot scale infinitely, the exposure field drops from 26x33 mm to 26x16.5 mm. To produce large GPUs or high-end server processors that exceed this half-field size, foundries must execute 'field stitching'—exposing one half of the die and then mathematically aligning the adjacent exposure down to single-nanometer precision. A misalignment of just 1.5 nanometers can ruin an entire wafer, making stitch-line yield management the single biggest operational challenge in 2026 semiconductor manufacturing.
Report check Tool suppliers claim single-exposure High-NA will accelerate fab cycle times by 25% by eliminating multi-patterning steps. What is verified: critical dimensions down to 8 nanometer metal pitch are printed reliably in test test-patterns. What is disputed: operational cost savings. Given that each scanner exceeds $350 million and reticle replacement costs are doubled due to smaller fields, independent analysts project overall wafer costs will rise by 18% to 22% during the initial two-year rollout.
Open questions Will chip architectures permanently fracture into smaller chiplet designs simply to avoid the stitching penalty of High-NA tools, effectively letting lithography optical constraints dictate processor system architecture?