NEW YORK — What happened: Major semiconductor fabrication plants have officially initiated commercial trial runs for sub-nanometer Gate-All-Around (GAA) transistor architectures. This milestone marks a definitive shift away from traditional FinFET designs, which had reached their scaling limits at the tightest pitches.
Why it matters: As transistor scaling slows, performance gains have increasingly relied on architectural overhauls rather than simple shrinks. GAA allows gate material to wrap completely around the channel, drastically reducing current leakage and improving switching speeds at ultra-low voltages.
Deep dive: In a FinFET, the gate controls the channel from three sides. GAA replaces the flat fin with vertical silicon nanosheets or nanowires surrounded entirely by the gate material. This provides superior electrostatic control. However, manufacturing these multi-bridge channel structures requires extreme precision in atomic-layer etching and deposition, leading to initial yield challenges that foundries have spent years mitigating.
Report check (claims vs what is verified vs still rumor): Press releases claim standard density scaling of over 40 percent generation-over-generation. Independent analysis verifies that early wafers show the expected leakage reduction, but commercial-grade defect densities for high-volume production remain largely unverified by third-party chip designers.
Open questions: How will thermal dissipation behave when these dense logic dies are packaged in multi-die configurations? Will the cost per transistor finally start rising instead of falling?