NEW YORK — What happened: Major chip manufacturers have begun volume production using backside power delivery networks (BSPDN), moving power routing lines to the opposite side of the silicon wafer from the active transistor gates.
Why it matters: As transistors shrink below two nanometers, routing both signal wires and power lines through the same top-side metal layers creates severe electrical resistance and thermal bottlenecks. BSPDN separates power delivery from data routing, significantly reducing voltage drop and improving power efficiency by up to fifteen percent.
Deep dive: Traditional chip design handles power and data on the same multi-layered metal stack on top of the silicon. This causes congestion, much like building power lines and data cables inside the exact same narrow highway lanes. By flipping the wafer and routing power through the backside, engineers create a dedicated highway for electricity. This architectural shift requires entirely new manufacturing steps, including ultra-precise wafer thinning and the creation of microscopic through-silicon vias.
Report check (claims vs what is verified vs still rumor): Press releases claim generational leaps in performance per watt. Independent teardowns verify that the structural architecture is present in late-2026 enterprise silicon samples. It remains rumor whether early yields will keep consumer chip prices stable or if manufacturing overhead will inflate retail costs.
Open questions: How will thermal dissipation behave over long-term high-load scenarios now that the top side is free of bulky power lines but potentially denser in active compute units?