NEW YORK — What happened: Major fabrication plants have begun high-volume manufacturing of client and server processors that route electrical power through the underside of the silicon wafer, rather than sharing the top-side routing layers with data signals.
Why it matters: As transistor gates shrink to atomic scales, the metal wires carrying power and data on the top layer of a chip have become severely congested. This congestion causes electrical resistance, voltage droop, and thermal bottlenecks that limit performance gains.
Deep dive: Traditionally, transistors were built on the silicon substrate, and all metal interconnect layers—both power and signal—were stacked on top. By moving power delivery to the back of the wafer, manufacturers free up the front-side routing layers strictly for data signals. This separation drastically reduces RC delay (resistance-capacitance delay), allows cleaner power delivery, and enables denser transistor packing without thermal throttling.
Report check (claims vs what is verified vs still rumor): Makers claim up to a 15 percent performance boost at the same power draw, or a 30 percent power reduction at the same frequency. Independent teardowns verify that the backside power structures are present in current production steppings. Rumors regarding ultimate yield rates and manufacturing costs remain closely guarded by the foundry operators.
Open questions: How will these complex dual-sided manufacturing processes scale as foundries transition to sub-2nm gate-all-around architectures, and will the yield costs trickle down to consumer hardware pricing?