What happened
Major commercial foundries have officially ramped up production on nodes utilizing backside power delivery networks (BSPDN), moving power routing to the underside of the silicon wafer while leaving the top layer exclusively for data signals.
Why it matters
As transistors shrink past the 2-nanometer threshold, traditional power lines running on the same plane as signal wires created massive electrical resistance and thermal bottlenecks. By routing power from the back, engineers eliminate this congestion, yielding double-digit performance increases and substantial power savings without changing transistor architectures.
Deep dive
In traditional chip design, power and data fight for the same microscopic real estate on the top surface of the wafer. This congestion causes voltage drop and heat accumulation. BSPDN thins the silicon substrate and punches microscopic vias through it to deliver electricity directly to the base of the transistors. This frees up top-layer routing channels, significantly reducing signal interference and allowing clock speeds to climb cleanly.
Report check (claims vs what is verified vs still rumor)
Industry press releases claim a universal 30 percent boost in efficiency. Independent teardowns and technical conference papers verify a 15 to 22 percent improvement in power efficiency depending on workload, while rumors of immediate price parity with older nodes remain unverified.
Open questions
Will the yield rates for backside via manufacturing remain stable as production scales to hundreds of millions of mobile chips, and how will this affect thermal management in fanless devices?